Metal contamination of semiconductor substrates negatively affects device characteristics of the product. For example, when heavy metals such as Fe and Ni enter Si, they create deep levels in the band gap, function as carrier trap centers and Generation-Recombination Centers, cause p-n junction leaks in devices, and diminish the lifetime of silicon. Accordingly, a highly reliable method of evaluating metal contamination in semiconductor substrates is needed to provide high-quality semiconductor substrates with little metal contamination.
Various methods have been proposed and put to practical use as methods of evaluating metal contamination in semiconductor substrates. Of these, the DLTS method (see U.S. Pat. Nos. 3,859,585 and 4,437,060, which are expressly incorporated herein by reference in their entirety) has high sensitivity. As a result, it has frequently been used as silicon wafers have become increasingly clean, particularly in recent years.
A brief overview of the conventional DLTS method will be given below. The example of a sample in which a 1 mm2 Schottky diode has been formed on p-type CZ silicon will be given with reference to the drawings below.
1) A reverse voltage (VR) forming a depletion layer and a weak voltage (V1) of close to 0 V to trap carriers in the depletion layer (the conditions under which the voltages are applied to the diode serving as the sample are shown in the top part of FIG. 12; in the figure, VR=+5V and V1=+1V) are alternatingly and cyclically applied to a semiconductor junction (Schottky junction or p-n junction) formed on a semiconductor sample to be evaluated.
2) The transient response of the capacitance of the diode that is generated in response to the voltage is measured (see the bottom part of FIG. 12).
3) The application of the voltage and the measurement of the capacitance in 1) and 2) above are conducted while varying the sample temperature over a prescribed temperature range. In the case of silicon, the temperature is generally varied over a range of 30 to 300K. The transient response of the capacitance is dependent on temperature. FIG. 13 shows a schematic diagram of such temperature dependence.
In this process, the DLTS signal (ΔC) is defined as follows:ΔC=C(t1)−C(t2)  (1)
In Equation (1) above, C(t1) denotes the capacitance at a time t1 after a prescribed period has elapsed following application of the voltage, and C(t2) denotes the capacitance at a time t2 after a prescribed period has elapsed following measurement of C(t1). In recent years, a method (lock-in type) has been widely used in which a lock-in amplifier is used to take the difference between the integrated values of the first half and second half of the transient response as the DLTS signal. Since the DLTS signal ΔC is a minute signal, the value ΔC that is measured is normally inputted to a computer and an average value is obtained for each temperature. However, there are many cases in which the temperature sweep is conducted linearly and the average value of ΔC obtained over a range of T±0.5 to 1 [K] is adopted as the ΔC at a temperature T [K].
When a deep level is present in the depletion layer formed by applying the reverse voltage (VR), a DLTS spectrum such as that shown in FIG. 14 can be obtained by plotting the relation between the DLTS signal ΔC and the temperature. FIG. 14 is a DLTS spectrum obtained by measuring p-type CZ silicon under two sets of conditions of a measurement frequency e=54.25/s and e=542.5/s. The reason why a spectrum of the form shown in FIG. 14 was obtained is that the speed at which the carriers were released was dependent on temperature as set forth below.
Low temperature: ΔC≈0 because the release of carriers from deep levels was slow.
High temperature: The release of carriers from deep levels was rapid, ending completely before t=t1, resulting in ΔC≈0.
Due to the above relation, there is dependence on the characteristics of deep levels (activation energy Ea, carrier capture cross-section area σ) and on the measurement conditions, and a peak in ΔC occurs at a prescribed temperature. In FIG. 14, since data processing was conducted according to Equation (1), the peak is downward (downwardly convex). There is also data processing in which ΔC=C(t2)−C(t1). In that case, the signal based on the deep level will be upwardly convex.
From the height of the peak in the DLTS spectrum thus obtained, the concentration (NT) of the deep level can be calculated from Equation (2) below, for example:NT≈2*ND*ΔCMAX/C∞(/cm3)  (2)
In the above equation, ND denotes the dopant concentration, ΔCMAX denotes the intensity of the DLTS signal at the peak position temperature, and C∞ denotes the capacitance of the depletion layer once the release of carriers from deep levels has nearly ended following application of VR. Accordingly, one obtains C∞=C(V=VR, t=∞).
When DLTS measurement is conducted while varying the ratio of t1/t2, the DLTS peak position shifts correspondingly.
When that happens, it becomes possible to calculate the emission rate e of carriers from Equations (3) and (4) below based on measurement conditions t1 and t2.τ=(t2−t1)/log(t2/t1)  (3)e=1/τ  (4)
By plotting the inverse 1/T of the peak position (temperature) T on the X axis and plotting e/T2 on the Y axis in a so-called Arrhenius plot, it is possible to obtain the energy level (ET) of the deep level from the slope (y-intercept) of the plot. That is because the relation of Equation (5) below exists between the various characteristic values:ln(e/T2)=ln(γσ)·Eact/kT  (5)In the above equation, k denotes the Boltzmann constant, and γ and Eact are as set forth below. In the case of an n-type substrate (in which the majority carriers are electrons):γ=1.9E20 [cm−2s−1K−2]Eact=Ec−ET [eV]In the case of a p-type substrate (in which the majority carriers are holes):γ=1.8E21 [cm−2s−1K−2]Eact=Ec−EV [eV](In the above, EC denotes the lower edge of the conduction band and EV denotes the upper edge of the valence band.)
The identity (type of contaminating metal) of the deep level detected by these measurements can be specified by comparison with libraries of Arrhenius plots based on the measurement results of DLTS given in the past reference and literature, and libraries of Arrhenius plots individually prepared by collecting the measurement results of DLTS of semiconductor substrates into which defects and metal contaminants have been intentionally introduced. For example, in FIG. 14, in the two sets of conditions of measurement frequencies of e=54.25/s and e=542.5/s, DLTS signal peaks were detected at positions of 52 k and 60 k, respectively. FIG. 15 is the result of preparing an Arrhenius plot of the relation between e and the peak position (temperature) obtained in the measurement of FIG. 14 and comparing it to a library built into the measurement apparatus. From FIG. 15, it will be understood that there is a high possibility of the DLTS signal detected in FIG. 14 being due to the pair Fe—B. Based on these results, it is possible to specify the contaminating metal as Fe.
As shown in FIG. 15, when a large quantity of contaminant metal is contained in a semiconductor substrate, the DLTS signal from the deep level will be quite large, and compared to it, the effect of the baseline slope or undulation will be quite small and can be ignored, making it easy to detect the peak. However, as the performance of semiconductor devices has improved in recent years, the cleaning (the reduction of the concentration of metal impurities) of semiconductor substrates such as silicon wafers has progressed. Thus, there is a need for even greater sensitivity to evaluate trace quantities of metal impurities by the DLTS method. However, in clean semiconductor substrates, the quantity of metal impurities causing the formation of deep levels is small, rendering the DLTS signal extremely weak. In such cases, the magnitude of baseline slope and undulation components unrelated to the emission of carriers by deep levels is large, that is not negligible relative to the intensity of the actual DLTS signal due to deep levels, hindering detection of the position and height of peaks with good precision. When baseline undulation or the like is present, in addition to a high level of so-called white noise, it impedes identification of the signal (peak). As a countermeasure to these baseline slopes and undulations, there exists the method of analysis of simply connecting the two shoulders of the signals due to deep levels with a straight line and using this straight line as a baseline. However, when multiple peaks appear in overlapping fashion (or the possibility of their appearing in this manner exists), the procedure of simply connecting the two shoulders of the peaks with a line is of doubtful reliability. There are also cases in which the baseline contains undulation that does not lend itself to approximation with a simple straight line. Thus, this method presents the risk of considerable error.
There is a need to achieve further sensitivity in the evaluation of metal contamination in semiconductor substrates by the DLTS method, as set forth above.